How does the FSM react after an error or timeout ata stage?
A.
stops
B.
retries until successful
C.
continues
D.
retries that stage at scheduled intervals
E.
raises faults and continues
How does the FSM react after an error or timeout ata stage?
How does the FSM react after an error or timeout ata stage?
A.
stops
B.
retries until successful
C.
continues
D.
retries that stage at scheduled intervals
E.
raises faults and continues