Which of the following chipsets is responsible for controlling the data flow between a PATA optical
drive and the processor?
A.
Northbridge
B.
BIOS
C.
Southbridge
D.
DMA controller
Explanation:
Which of the following chipsets is responsible for controlling the data flow between a PATA optical
drive and the processor?
Which of the following chipsets is responsible for controlling the data flow between a PATA optical
drive and the processor?
A.
Northbridge
B.
BIOS
C.
Southbridge
D.
DMA controller
Explanation: