Which three statements are correct about data paths in the SPARC M5-32 server?
A.
Within a DCU, a CPU talks to another CPU directly by using the coherency switch. The SSB is not needed.
B.
From one DCU to a different DCU, an even talks with only another even (same for odd) and hops to the odd-numbered board, if needed, on the destination DCU.
C.
From one DCU to a different DCU, all CPUs can access all PCIe slots In the destination DCU directly in one hop.
D.
A DCU can communicate data only with other DCUs via the BX ASICs on the SSB.
E.
From one DCU to a different DCU, even CPUs can access ail the odd PCIe slots in the destination DCU directly in one hop.
Explanation:
http://docs.oracle.com/cd/B10501_01/server.920/a96533/statspac.htm